2.4. Sky130 Technology Library

Hammer supports the Skywater 130nm Technology process. The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit (PDK) and related resources, which can be used to create manufacturable designs at SkyWater’s facility.

2.4.1. PDK Setup

The Skywater 130nm PDK files are located in a repo called skywater-pdk. A tool called Open-PDKs (open_pdks) was developed to generate all the files typically found in a PDK. Open-PDKs uses the contents in skywater-pdk, and outputs files to a directory called sky130A. PDK Install

# create a root directory that will contain all PDK files and supporting tools (install size is ~42GB)
export PREFIX=/path/to/install/root
mkdir -p $PREFIX

# install magic via conda, required for open_pdks
conda create -y -c litex-hub --prefix $PREFIX/.conda-signoff magic
export PATH=$PREFIX/.conda-signoff/bin:$PATH

# clone required repos
git clone https://github.com/google/skywater-pdk.git
git clone https://github.com/RTimothyEdwards/open_pdks.git

# install Sky130 PDK via Open-PDKs
#    we disable some install steps to save time
cd $PREFIX/open_pdks
./configure \
    --enable-sky130-pdk=${PREFIX}/skywater-pdk/libraries --prefix=$PREFIX \
    --disable-gf180mcu-pdk --disable-alpha-sky130 --disable-xschem-sky130 --disable-primitive-gf180mcu \
    --disable-verification-gf180mcu --disable-io-gf180mcu --disable-sc-7t5v0-gf180mcu \
    --disable-sc-9t5v0-gf180mcu --disable-sram-gf180mcu --disable-osu-sc-gf180mcu
make install

This generates all the Sky130 PDK files and installs them to $PREFIX/share/pdk/sky130A

Now in your Hammer YAML configs, point to the location of this install:

technology.sky130.sky130A: "<PREFIX>/share/pdk/sky130A"

2.4.2. SRAM Macros

If you are using SRAMs in your design, such as for the Chipyard Sky130 tutorial, you will require a set of SRAM macros. The Sky130 PDK did not come with it’s own SRAM macros, so these have been generated by various third-party contributors. Hammer is compatible with Sky130 SRAM macros generated by Sram22 and OpenRAM, but starting with Hammer v1.0.2 only Sram22 macros will be supported. To obtain these macros, clone their github repo:

git clone https://github.com/rahulk29/sram22_sky130_macros

Then set the respective Hammer YAML key:

technology.sky130.sram22_sky130_macros: "/path/to/sram22_sky130_macros"

Note that the various configurations of the SRAMs available are encoded in the file sram-cache.json. To modify this file to include different configurations, or switch to using the OpenRAM SRAMs, navigate to ./extra/[sram22|openram] and run the script ./sram-cache-gen.py for usage information.

2.4.3. IO Library

The IO ring required by efabless for MPW/ChipIgnite can be created in Innovus using the sky130_fd_io and sky130_ef_io IO cell libraries. Here are the steps to use them:

  1. extra/efabless_template.io is a template IO file. You should modify this by replacing the <inst_path>s with the netlist paths to your GPIO & analog pads. DO NOT MODIFY ANY POSITIONS OR REPLACE CLAMP CELLS WITH IO CELLS.

    a. For pad assignment: the ordering in the instance lists are from left to right (for top/bottom edges) and bottom to top (for left/right edges).

    b. Refer to this documentation for how to configure the pins of the IO cells (not exhaustive).

    c. Your chip reset signal must go thru the xres4v2 cell. Since this is in your netlist, you must remove the cell=... instantiation from your IO file (it is only in the template for clarity) and update the inst name. Otherwise a separate instance will be placed instead.

    d. The ENABLE_INP_H pin must be hard-tied to TIE_HI_ESD or TIE_LO_ESD. Since this is at a higher voltage, verify that this is routed as a wire only (no buffers can be inserted).

    e. ENABLE_H must be low at chip startup before going high. Absent using the power detector cell from the NDA IO library, you may elect to connect this to a reset signal.

    f. This template file does not contain dedicated clamps for the VSWITCH or VCCHIB supplies (following Caravel). EFabless provides a sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_slice_20um slice in open_pdks that replaces a standard 20um spacer with a slice that connects VCCHIB and VCCD together, and VSWITCH and VDDIO together. Note that this slice cannot be placed immediately to the right (in the R0 orientation) of a *_clamped3_pad cell, because otherwise they will create a supply short. The template IO file contains normal 20um spacer slices explicitly placed at these critical locations, and the provided hook instantiates the connect slice in place of the standard 20um spacer. This can be modified if desired. Caravel distributes the *connect* slices across the bottom edge of the padframe.

  2. Then, in your design YAML file, specify your IO file with the following. The top-level constraint must be exactly as below:

    technology.sky130.io_file: <path/to/ring.io>
    technology.sky130.io_file_meta: prependlocal
    path: Top
    type: toplevel
    x: 0
    y: 0
    width: 3588
    height: 5188
      left: 249.78
      right: 249.78
      top: 252.08
      bottom: 252.08
  3. In your CLIDriver, you must import the following hook from the tech plugin and insert it as a post_insertion_hook after floorplan_design.

    from hammer.technology.sky130 import efabless_ring_io

    In addition, to ensure ties to TIE_HI_ESD / TIE_LO_ESD are preserved during synthesis, a post_insertion_hook to init_environment should be added to dont_touch the IO cells

    def donttouch_iocells(x: HammerTool) -> bool:
        x.append('set_dont_touch [get_db insts -if {.base_cell.name == sky130_ef_io__*}] true')
        return True
  4. If you want to use the NDA s8iom0s8 library, you must include the s8io.yml file with -p on the hammer-vlsi command line, and then change the cells to that library in the IO file. Net names in the hook above will need to be lower-cased.

  5. DRC requires a rectangle of areaid.lowTapDensity (GDS layer 81/14) around the core area to check latchup correctly. Currently, this is not yet implemented in Hammer, and will need to be added manually in a GDS editor after GDS streamout.

2.4.4. NDA Files

The NDA version of the Sky130 PDK is only required for Siemens Calibre to perform DRC/LVS signoff with the commercial VLSI flow. It is NOT REQUIRED for the remaining commercial flow, as well as the open-source tool flow. Therefore this NDA PDK is not used to generate a GDS.

If you have access to the NDA repo, you should add this path to your Hammer YAML configs:

technology.sky130.sky130_nda: "/path/to/skywater-src-nda"

We use the Calibre decks in the s8 PDK, version V2.0.1, see here for the DRC deck path and here for the LVS deck path.

2.4.5. Resources

The good thing about this process being open-source is that most questions about the process are answerable through a google search. The tradeoff is that the documentation is a bit of a mess, and is currently scattered over a few pages and Github repos. We try to summarize these below.


  • Sram22 pre-compiled macros

    • Various pre-compiled sizes of SRAM macros to support Hammer Sky130 flow

  • Sram22

    • Open-source SRAM generator

    • Currently only supports the Sky130 process

    • Very much under development, and some parts currently require commercial tools (for LEF and LIB generation)

  • OpenRAM pre-compiled macros

    • Precompiled sizes are 1kbytes, 2kbytes and 4kbytes

  • OpenRAM

    • Open-source static random access memory (SRAM) compiler

Git repos: