Power
===============================

Hammer supports RTL, post-synthesis, and post-P&R power analysis. It provides a simple API to add flags to the power tool call and automatically passes in collateral to the power tool from the other tool steps.
This action requires a tool plugin to implement ``HammerPowerTool``.

Power Setup Keys
-------------------------------

* Namespace: ``vlsi.core``

    * ``power_tool``
        * Module of the power tool, e.g. ``hammer.power.voltus``

Simulation Input Keys
-------------------------------

* Namespace: ``power.inputs``

    * ``database`` (str)

        * Path to the place and route database of the design to be analyzed. This path may be relative to the directory in which ``hammer-vlsi`` is called.

    * ``tb_name`` (str)

        * The name of the testbench/test driver in the simulation.

    * ``tb_dut`` (str)

        * Hierarchical path to the to top level instance of the "dut" from the testbench.

    * ``spefs`` ([str])

        * List of paths to all spef (parasitic extraction) files for the design. This list may include a spef file per MMMC corner. Paths may be relative to the directory in which ``hammer-vlsi`` is called.

    * ``waveforms`` ([str])

        * List of paths to waveforms to be used for dynamic power analysis. Paths may be relative to the directory in which ``hammer-vlsi`` is called.

    * ``start_times`` ([TimeValue])

        * List of analysis start times corresponding to each of the ``waveforms`` used for dynamic power analysis.

    * ``end_times`` ([TimeValue])

        * List of analysis end times corresponding to each of the ``waveforms`` used for dynamic power analysis.

    * ``saifs`` ([str])

        *  List of paths to SAIF (activity files) for dynamic power analysis. Generally generated by a gate-level simulation. Paths may be relative to the directory in which ``hammer-vlsi`` is called.

    * ``extra_corners_only`` (bool)

        * If overridden to ``true``, the power tool will report for only the extra MMMC corners, saving runtime. The typical use case is to only report power and rail analysis for a typical/nominal corner.

    * ``input_files`` ([str])
        * A list of the paths to the design inputs files (HDL or netlist) for power analysis.

    * ``sdc`` (str)
        * Path to SDC input file.

    * ``report_configs`` ([dict])
        * List of report configs that specify ``PowerReport`` structs.

    * ``level`` (FlowLevel)
        * Power analysis mode for different levels of the VLSI flow. The available options are ``rtl``, ``syn``, and ``par``.

    * ``top_module`` (str)
        * Top RTL module for power analysis.

Power Inputs
-------------------------------

Hammer's power analysis can be run with an RTL input, or post-synthesis or post-place-and-route (and with corresponding simulations).
Auto-translation of of Hammer IR to the power tool from those outputs are accomplished using the ``sim-rtl-to-power``, ``syn-to-power``, ``sim-syn-to-power``, ``par-to-power``, and ``sim-par-to-power`` actions, as demonstrated below.
The required files for power analysis (database, SAIF, SPEF, etc.) are generated and piped to the power tool from the pre-requisite action's outputs.

Power Outputs
-------------------------------

The power tool outputs static and active power estimations into the ``OBJ_DIR/power-rundir/`` directory. Exact report format may vary by tool used.

Power Commands
-------------------------------

RTL Power Analysis:

* RTL Sim

    * ``hammer-vlsi -e env.yml -p config.yml --obj_dir OBJ_DIR sim-rtl``

* Simulation to Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/sim-rundir/sim-rtl-output.json -o OBJ_DIR/sim-rtl-to-power_input.json --obj_dir OBJ_DIR sim-rtl-to-power``

* Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/sim-rtl-to-power_input.json --obj_dir OBJ_DIR power-rtl``

Post-synthesis Power Analysis:

* Syn to Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/syn-rundir/syn-output.json -o OBJ_DIR/syn-to-power_input.json --obj_dir OBJ_DIR syn-to-power``

* Syn to Simulation

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/syn-rundir/syn-output.json -o OBJ_DIR/syn-to-sim_input.json --obj_dir OBJ_DIR syn-to-sim``

* Post-Syn Gate Level Sim

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/syn-to-sim_input.json --obj_dir OBJ_DIR sim-syn``

* Simulation to Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/sim-rundir/sim-syn-output.json -o OBJ_DIR/sim-syn-to-power_input.json --obj_dir OBJ_DIR sim-syn-to-power``

* Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/syn-to-power_input.json -p OBJ_DIR/sim-syn-to-power_input.json --obj_dir OBJ_DIR power-syn``

Post-P&R Power Analysis:

* P&R to Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/par-rundir/par-output.json -o OBJ_DIR/par-to-power_input.json --obj_dir OBJ_DIR par-to-power``

* P&R to Simulation

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/par-rundir/par-output.json -o OBJ_DIR/par-to-sim_input.json --obj_dir OBJ_DIR par-to-sim``

* Post-P&R Gate Level Sim

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/par-to-sim_input.json --obj_dir OBJ_DIR sim-par``

* Simulation to Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/sim-rundir/sim-par-output.json -o OBJ_DIR/sim-par-to-power_input.json --obj_dir OBJ_DIR sim-par-to-power``

* Power

    * ``hammer-vlsi -e env.yml -p config.yml -p OBJ_DIR/par-to-power_input.json -p OBJ_DIR/sim-par-to-power_input.json --obj_dir OBJ_DIR power-par``